1. Field of the Invention
The present invention relates to the formation of static random access memories (SRAMs) in a manner that allows the memories to have low standby power usage.
2. Description of the Related Art
Reduced geometry integrated circuit designs are adopted to increase the density of devices within integrated circuits in hopes of increasing performance and decreasing the costs of the integrated circuits. Modem integrated circuit memories, including DRAMs, SRAMs, ROMs, EEPROMS, etc., are prominent examples of the application of this strategy. The density of memory cells within integrated circuit memories continues to increase, accompanied by a corresponding drop in the cost per bit of storage within such devices. Increases in density are accomplished by forming smaller structures within devices and by reducing the separation between devices or between the structures that make up the devices. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced device sizes or are necessary to maintain performance when such smaller design rules are implemented. As an example, the reduced operating voltages used in many conventional integrated circuits are made possible by improvements in design, such as reduced gate oxide thickness and improved tolerance controls in lithographic processing. On the other hand, reduced design rules make reduced operating voltages essential to limit the effects of hot carriers generated in small size devices operating at higher, previously conventional operating voltages.
Another operating parameter affected by altering the design rules used to manufacture an integrated circuit memory device is the power consumption within static random access memories (SRAMs). SRAMs are frequently used in applications which require low power consumption when the SRAM is in its standby state. For example, portable computing devices require low power consumption at all times to prolong battery life. Other computing applications require low power operation in some operating states, such as desk top computers which have a low power consumption "sleep" state that the computer enters after an extended period of inactivity. For such a computer, or at least for some components of such a computer like the modem, it is desirable to keep as much of the operating state of the computer as is practical in integrated circuit memory (as opposed to hard disk or mass storage memory) so that the computer can rapidly resume normal operation after being awoken from its sleep state. To maintain low power consumption, it is important to use SRAM for storage of the operating state of the computer, because other types of memory use too much power (DRAM) or are not suited for the purpose (EEPROMs, flash). As SRAM density increases due to the application of reduced design rules, it becomes more difficult to maintain acceptably low levels of power consumption. For the reduced design rules, the devices within the SRAM become smaller and there is a tendency for the smaller devices to exhibit an increased level of leakage, so that the leakage for each cell tends to increase. This problem is compounded for higher density SRAM designs because the number of cells in the SRAM increases for the increased design rules so that the higher cell leakage is multiplied by the larger number of cells. It is accordingly important to reduce the level of charge leakage in SRAM cells to make the higher density SRAMs more useful for low power consumption applications.
Typical SRAM designs include two or four MOS transistors coupled together in a latch configuration having two charge storage nodes for storing the charge states which correspond to the data stored in the cell. The SRAM cell includes two pull down transistors and two load devices which may be polysilicon load resistors but are more typically thin film transistors in modem SRAMs. Each of the charge storage nodes includes at a connection between a corresponding pull down transistor and a corresponding one of the load devices and each of the charge storage nodes is coupled to the gate electrode of the other pull down transistor in the conventional latch configuration. Data are read out of the conventional SRAM cell in a non-destructive manner by selectively coupling each charge storage node to a corresponding one of a pair of complementary bit lines. The selective coupling is accomplished by a pair of pass transistors, each pass transistor connected between one of the charge storage nodes and the corresponding one of the complementary bit lines. Word line signals are provided to the gates of the pass transistors to switch the pass transistors ON during data read operations. Charge flows through the ON pass transistors to or from the charge storage nodes, discharging one of the bit lines and charging the other of the bit lines. The voltage changes on the bit lines are sensed by a differential amplifier. For the SRAM cell's latch to remain stable during such a data reading operation, at least one of the charge storage nodes within the SRAM must charge or discharge at a faster rate than charge flows from or to the corresponding bit line. This control is typically maintained in part by making the channel of the pass transistor connected to the particular charge storage node narrower and/or longer than the channel of at least one of the SRAM pull-down transistors having a drain connected to the particular charge storage node. This geometry allows more current to flow through the at least one SRAM pull-down transistor than through the corresponding pass transistor; consequently, the charge storage node charges or discharges faster than the corresponding bit line discharges or charges.
During standby operation when the SRAM is not performing read or write operations, charge tends to leak from the charge storage nodes in a manner that could eventually result in loss of data from the cells of the SRAM or could render data within some of the cells to become indeterminate. To address this problem, SRAMs are designed to maintain the potential on the charge storage node by causing charge to be provided to the charge storage node, preferably at a very slow average rate that is well matched to the level of charge leakage from the charge storage node. SRAM cells provide two load devices each connected between a charge storage node and the high reference potential. Charge flows either constantly or intermittently from the high reference potential through the load devices to the respective charge storage nodes to replace the charge that leaks from the charge storage node. Because operation of the load devices, whether active or passive, uses power at all times in which data are stored on the SRAM, reduction of the power consumption by the load devices has been studied in attempts to reduce the power consumption of higher density SRAMs. For example, U.S. Pat. No. 5,514,880 to Nishimura, et al., entitled "Field Effect Thin-Film Transistor for an SRAM with Reduced Standby Current," describes a variety of different designs intended to control the leakage through thin film transistors used as the load devices of an SRAM.
With continuing needs to reduce the power consumption and increase the integration density of SRAMs, there remains a further need to reduce the power consumption of individual SRAM cells and of complete SRAM circuits.